This invention relates generally to integrated circuit devices and their fabrication, and more particularly, to integrated circuit transistors and methods for their fabrication.
A number of potential problems are caused by the high circuit element density of today""s integrated circuits. For example, densely packed field-effect transistors have relatively short channel lengths, resulting in increased potential for punchthrough effects. Also, the correspondingly shallow drain and source junction depths can result in junction spiking effects, in which metallization layers penetrate drain and source diffusions. The short channel lengths also result in higher electric field strengths, which in turn cause deleterious hot carrier effects. Reduced device geometries increase capacitive coupling between source/drain regions and the body of the transistor, resulting in degraded device performance and signal transmission characteristics. In the case of CMOS technology, parasitic thyristors and associated latchup effects arise. These and other fundamental problems must be addressed by the circuit designer and process engineer.
In accordance with an embodiment of the present invention, an integrated circuit formed on a monocrystalline semiconductor substrate is provided. The integrated circuit includes a monocrystalline first semiconductor region of a first conductivity type overlying the substrate. An electrical isolation region overlies the substrate and substantially laterally adjoins the first region. Second and third semiconductor regions of a second conductivity type overly the electrical isolation region and substantially laterally adjoin the first region. The first region may include an epitaxial region contiguous with the substrate. The electrical isolation region may include a dielectric layer overlying and contiguous with the substrate, with the second and third regions overlying and being contiguous with the dielectric layer. The second and third regions may include both substantially polycrystalline and substantially monocrystalline semiconductor material. The second and third regions and the first region may each consist essentially of the same semiconductor material, and the first region and the substrate may consist essentially of the same semiconductor material.
In accordance with another embodiment of the present invention, a field effect transistor is provided. The transistor includes a monocrystalline semiconductor body region and a monocrystalline semiconductor channel region overlying the body region. First and second semiconductor source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region. The first and second semiconductor source/drain regions may include substantially polycrystalline semiconductor regions and/or substantially monocrystalline semiconductor regions. The transistor may include a dielectric region underlying the source/drain regions to electrically isolate these regions from the body region. The transistor may further include a second dielectric region overlying the channel region, and a conductive gate region overlying the second dielectric region.
In accordance with an embodiment of the present invention, a method of fabricating an integrated circuit device on a monolithic semiconductor substrate is provided. The method includes forming a patterned dielectric layer on the substrate. The dielectric layer selectively covers some portions of the substrate and leaves an exposed portion of the substrate. A first, substantially monocrystalline semiconductor layer is then formed on the exposed portion of the substrate, and a second semiconductor layer is formed on the dielectric layer, with the first and second layers being substantially contiguous. The second semiconductor layer is doped to provide a conductivity type opposite that of the first semiconductor layer. Formation of the first semiconductor layer may include forming an epitaxial semiconductor layer on the exposed portion of the substrate, and may include the same semiconductor material as the substrate. Formation of the first and second semiconductor layers may be performed substantially simultaneously, and may be formed from essentially the same semiconductor material.